Liquid crystal display (LCD) devices have been actively studied and researched owing to advantageous characteristics such as high contrast ratio, fine gray level, high picture quality and low power consumption. An LCD device is suitable for ultra-thin display device such as a wall-mountable television. The LCD device has attracted great attention as a new display device that can substitute for CRT in that the LCD device has thin profile, lightness in weight and low power consumption. As a result, the LCD device is also used for a display device of a notebook computer operated by a battery.
Generally, the LCD device includes a thin film transistor array substrate having a thin film transistor TFT and a pixel electrode in each pixel region defined by intersecting gate and data lines at right angles, a color filter array substrate having a color filter layer and positioned in opposition to the thin film transistor array substrate, and a liquid crystal layer having a dielectric anisotropy, formed between the thin film transistor array substrate and the color filter array substrate. When a voltage is applied to the corresponding pixel region by switching the thin film transistors TFT in the pixel regions of hundreds of thousands by address lines for selection of the pixel region, so that the LCD device is operated.
The color filter array substrate and the thin film transistor array substrate are bonded to each other by a sealant such as epoxy resin. Also, a driving circuit of a PCB (Printed Circuit Board) is connected with the thin film transistor array substrate by a TCP (Tape Carrier Package). However, light leakage may occur due to the misalignment between the thin film transistor array substrate and the color filter array substrate. To overcome this problem, a TOC (TFT On Color Filter) type or COT (Color Filter on TFT) type LCD device, in which the color filter layer and the thin film transistor are formed on one substrate, has been researched and developed.
The COT type LCD device is formed by a method of forming a color filter layer and a thin film transistor on one substrate. As shown in FIG. 1F, the substrate 11 having the color filter layer and the thin film transistor formed thereon is divided into an active region and a pad region. The active region includes the color filter layer and the thin film transistor, and the pad region includes a gate pad 22 and a data pad 25.
On the active region of the substrate 11, there are a gate line (not shown), a data line DL 15, the thin film transistor TFT, an insulating interlayer 16, a black matrix layer 91, the color filter layer of R, G and B 92, an overcoat layer 93 and a pixel electrode 17. The gate line (not shown) intersects the data line 15 at right angles, to define a unit pixel region on the active region. The thin film transistor TFT is formed at the intersecting point of the gate and data lines, to switch signals. Also, the insulating interlayer 16 is formed on an entire surface of the substrate 11 including the thin film transistor TFT. The black matrix layer 91 is formed on the insulating interlayer 16 corresponding to the boundary between the pixel regions, to prevent light leakage. The color filter layer of R, G and B 92 is formed on the insulating interlayer 16 corresponding to the respective pixel regions. Then, the thick overcoat layer 93 is formed on the color filter layer 92, to planarize the entire surface of the substrate 11. The pixel electrode 17 is formed on the overcoat layer 93 of the pixel region, to be in contact with a drain electrode 15b. That is, the pixel electrode 17 is in contact with the drain electrode 15b through a first contact hole 95, wherein the first contact hole 95 is formed by removing the insulating interlayer 16 and the overcoat layer 93.
In addition, the active region includes a storage capacitor, comprised of a storage lower electrode 32, a storage upper electrode 35, and an insulating layer 13 interposed between the storage lower and upper electrodes 32 and 35. The storage capacitor maintains a voltage charged in a liquid crystal capacitor during a turn-off period of the corresponding thin film transistor TFT, so that it is possible to prevent the picture quality from being deteriorated by the parasitic capacitance. Also, the storage lower electrode 32 is formed in parallel with the gate line 12, whereby the storage lower electrode 32 receives am external voltage. Also, the storage upper electrode 35 is in contact with the pixel electrode 17 through a second contact hole 97.
The pad region includes the gate pad G-pad 22 extended from the gate line, and the data pad D-pad 25 extended from the data line. On the gate pad 22 and the data pad 25, there is a deposition layer of a gate insulating layer 13, the insulating interlayer 16 and the overcoat layer 93, wherein the deposition layer includes a pad open area 96. In addition, first and second transparent conductive layers 62 and 65 are formed on the deposition layer, wherein the respective first and second transparent conductive layers 62 and 65 are in contact with the gate pad 22 and the data pad 25 by the pad open area 96.
FIG. 1A to FIG. 1F are cross sectional views showing the fabrication process of the COT type LCD device according to the related art.
As shown in FIG. 1A, a low-resistance metal material is deposited on the substrate 11, and patterned by photolithography, thereby forming the gate line (not shown), a gate electrode 12a, the storage lower electrode 32 and the gate pad 22. Then, the gate insulating layer 13 is formed by depositing an inorganic insulating material such as silicon oxide SiOx or silicon nitride SiNx on the entire surface of the substrate 11 including the gate electrode 12a. After that, a semiconductor layer is deposited on the entire surface of the substrate 11, and then selectively removed, to form an active layer 14 on the gate insulating layer 13 above the gate electrode 12a. 
As shown in FIG. 1B, a low-resistance metal layer is deposited and patterned on the entire surface of the substrate 11 including the active layer 14, to form the data line 15, source and drain electrodes 15a and 15b, the storage upper electrode 35 and the data pad 25. The deposition layer of the gate electrode 12a, the gate insulating layer 13, the semiconductor layer 14 and the source and drain electrodes 15a and 15b forms the thin film transistor TFT. Subsequently, an inorganic insulating layer is deposited on the entire surface of the substrate 11 including the source and drain electrodes 15a and 15b, thereby forming the insulating interlayer 16.
Referring to FIG. 1C, an opaque organic material having a low dielectric constant is coated and patterned on the insulating interlayer 16, thereby forming the black matrix layer 91 overlapped with the thin film transistor TFT, the data line and the gate line. Subsequently, a color resist is regularly coated and patterned on the black matrix layer 91, whereby the color filter layer of R, G and B 92 is formed in the respective pixel regions.
As shown above, the thin film transistor TFT, the black matrix layer 91 and the color filter layer 92 are formed on one substrate.
Referring to FIG. 1D, an organic insulating material such as BCB (BenzoCycloButene) or photoacryl is coated on the entire surface of the substrate 11 including the color filter layer 92, thereby forming the overcoat layer 93. The overcoat layer 93 is formed to planarize the entire surface of the substrate 11, which is necessary for the COT type LCD device.
As shown in FIG. 1E, the overcoat layer 93, the insulating interlayer 16 and the gate insulating layer 13 are selectively removed to form the first contact hole 95, the second contact hole 97 and the pad open area 96. At this time, the first contact hole 95 exposes the drain electrode 15b, and the second contact hole 97 exposes the storage upper electrode 35. Also, the pad open area 96 exposes the gate pad 22 and the data pad 35.
As shown in FIG. 1F, a transparent conductive material is deposited and patterned on the overcoat layer 93, thereby simultaneously forming the pixel electrode 17 and the first and second transparent conductive layers 62 and 65. The pixel electrode 17 is in contact with the drain electrode 15b and the storage upper electrode 32 through the first and second contact holes 95 and 97. Also, the first and second transparent conductive layers 62 and 65 are in contact with the gate pad 22 and the data pad 25 through the pad open area 96.
Although not shown, a sealant is formed on the boundary between the active region and the pad region, wherein the sealant serves as an adhesive. In this state, the substrate 11 is bonded to another opposite substrate by the sealant, and then a liquid crystal layer is formed between the two substrates, thereby completing the LCD device.
However, the method for fabricating the COT type LCD device according to the related art has the following disadvantages.
In the method for fabricating the COT type LCD device according to the related art, the active layer, the data line and the source and drain electrodes are formed with the individual masks, thereby causing the complicated fabrication process and lowering the yield.
Also, the gate pad and the data pad are formed at the different layers. Accordingly, when opening the gate pad and the data pad, it may have a defect since the gate insulating layer, the insulating interlayer and a passivation layer are deposited on the gate pad, and only the insulating interlayer and passivation layer are deposited on the data pad.